The present invention relates to a semiconductor device, and more particularly, to a delay locked loop (DLL) having a duty cycle corrector (DCC).
In synchronous semiconductor memory devices such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), data are transferred to other devices in synchronization with a DLL clock signal (CLK_DLL) generated by delaying an external clock signal (CLK_EXT) inputted from an external circuit such as a memory controller. Examples of a clock synchronization circuit include a phase locked loop (PLL) and a delay locked loop (DLL). The DLL is widely used in semiconductor devices because it has low noise and can be implemented in a small area compared with the PLL.
The trend of the SDRAM is changing from a single data rate (SDR) SDRAM to a DDR SDRAM. The DDR SDRAM outputs data in synchronization with both rising edges and falling edges of an external clock (CLK_EXT). Therefore, the duty cycle of the DLL clock signal (CLK_DLL) should be 50:50 in order to maximize a valid data window of an output data in the semiconductor device. If the duty cycle of the DLL clock signal (CLK_DLL) is not maintained at 50%, an error corresponding to an offset from 50% reduces a timing margin of a high-performance memory system. Meanwhile, as the semiconductor device operates faster, the incoming external clock signal (CLK_EXT) becomes distorted, leading to clock skew. Due to the clock skew in the duty cycle, the DLL may operate abnormally. Further, the duty cycle problem may occur in the DLL in itself. Consequently, a desired DLL clock signal (CLK_DLL) may not be outputted, which degrades performance of the semiconductor device. Hence, a correct duty cycle of the DLL clock signal (CLK_DLL) is a critical factor for stable operations of the semiconductor device.
Therefore, the semiconductor device includes a duty cycle corrector (DCC) that corrects the duty cycle of the DLL clock signal (CLK_DLL) to 50:50 when the incoming external clock signal is asymmetric, or the DLL clock signal (CLK_DLL) is asymmetrically generated because the duty cycle is distorted by internal operations.
FIG. 1 is a block diagram of a conventional DLL having a DCC.
Referring to FIG. 1, a conventional DLL includes first and second clock buffers 11 and 12, first and second delay lines 13 and 14, a DCC phase mixer 15, a dummy DCC phase mixer 16, first and second delay replica models 17 and 18, first and second phase comparators 19 and 20, and first and second delay controllers 21 and 22.
The first and second clock buffers 11 and 12 buffer an external clock signal CLK_EXT and an external clock bar signal CLK_EXTB to generate first and second reference clock signals CLK_REF and CLK_REFB, respectively. The first delay line 13 generates a first delayed clock signal CLK_D1 by delaying the first reference clock signal CLK_REF corresponding to the external-clock signal CLK_EXT in response to a first delay control signal D_CTR1, and the second delay line 14 generates a second delayed clock signal CLK_D2 by delaying the second reference clock signal CLK_REFB corresponding to the external clock bar signal CLK_EXTB in response to a second delay control signal D_CTR2. The first delayed clock signal CLK_D1 has information on a rising edge of the external clock signal CLK_EXT, and the second delayed clock signal CLK_D2 has information on a falling edge of the external clock signal CLK_EXT2.
The DCC phase mixer 15 mixes phases of the first and second delayed clock signals CLK_D1 and CLK_D2 to generate a DLL clock signal CLK_DLL with a duty cycle of exactly 50%. The dummy DCC phase mixer 16 has the same structure as the DCC phase mixer 15 and generates a clock signal with a duty cycle of 50%.
The first delay replica model 17 delays the output signal CLK_DLL of the DCC phase mixer 15 through delay elements located in a clock path to generate a first feedback clock signal CLK_FDB1. The second delay replica model 18 has the same structure as the first delay replica model 17 and delays the output signal of the dummy DCC phase mixer 16 to generate a second feedback clock signal CLK_FDB2.
The first phase comparator 19 compares a phase of the first reference clock signal CLK_REF with a phase of the first feedback clock signal CLK_FDB1, and the first delay controller 21 controls a delay amount of the first delay line 13 according to the result of comparison of the first phase comparator 19. The second phase comparator 20 compares a phase of the first reference clock signal CLK_REF with a phase of the second feedback clock signal CLK_FDB2, and the second delay controller 22 controls a delay amount of the second delay line 14 according to the result of comparison of the second delay controller 22.
FIGS. 2A to 2C are timing diagrams of the first and second delayed clock signals CLK_D1 and CLK_D2 and the DLL clock signal CLK_DLL.
Specifically, FIG. 2A is a timing diagram of the DLL clock signal CLK_DLL before the locking operation of the DLL. As can be seen from FIG. 2A, the duty cycle of the DLL clock signal CLK_DLL is distorted.
FIG. 2B is a timing diagram of the DLL clock signal CLK_DLL when the DCC phase mixer 15 and the dummy DCC phase mixer 16 operate after the locking operation of the DLL. For convenience, the DCC phase mixer 15 and the dummy DCC phase mixer 16 will be referred to as a duty cycle corrector (DCC).
In further detail, as illustrated in FIG. 1, the first 0and second delayed clock signals CLK_D1 and CLK_D2 in FIG. 2A are independently locked by the control of the first and second delay lines 13 and 14, respectively. After the locking operation, the first and second delayed clock signals CLK_D1 and CLK_D2 coincide with each other at the rising edge and their duty cycles are opposite to each other, as illustrated in FIG. 2B. The DCC mixes the phase of the falling edge of the first delayed clock signal CLK_D1 and the phase of the falling edge of the second delayed clock signal CLK_D2 to generate the DLL clock signal CLK_DLL with a duty cycle of exactly 50%.
FIG. 2C is a timing diagram of the signals when a voltage bump phenomenon occurs, that is, a level of an external voltage (VDD) abruptly changes due to external and/or internal factors. As described above, the clock signals pass through the first and second delay lines 13 and 14 to generate the first and second delayed clock signals CLK_D1 and CLK_D2, respectively. In other words, since the first and second delayed clock signals CLK_D1 and CLK_D2 of FIG. 2B are generated through a different number of unit delays, their delay amounts are different from each other according to the external voltage (VDD). The unit delay is implemented using a NAND gate and its delay time changes according to the external voltage (VDD). For example, the delay time of the unit delay decreases when the external voltage (VDD) is high, while it increases when the external voltage (VDD) is low.
In the serious cases, as illustrated in FIG. 2C, the first and second delayed clock signals CLK_D1 and CLK_D2, which are delay-locked through a different number of unit delays, may have phases opposite to each other according to a voltage bump phenomenon. In this case, the duty cycle of the DLL clock signal CLK_DLL becomes worse or disappears and the DLL clock signal CLK_DLL becomes an unknown-state signal. Even though the DLL resumes the locking operation, a normal locking operation cannot be achieved-because the DLL clock-signal CLK_DLL disappears. Consequently, this leads to a defective semiconductor device.